1. ise map錯誤
看看你的時鍾引腳是不是真真接上時鍾了。如果接的不是時鍾,就會報這樣的錯
2. ise為什麼刪除一些輸入引腳會報錯
因為你信號列表裡面沒有這個信號 ,但又給他分配了一個管腳,他找不到管腳 應該連到哪個信號上去,所以就報錯了。
3. ISE Implementation是遇到的問題
我也遇到了這樣的問題,後來解決的辦法是,該加空格的地方一定要加空格,而不是把空格刪去!最關鍵的就是引腳後面的空格,一定要加!
4. xilinx ise錯誤求助
(1)編dcm時鍾控制測試程序時,設置好了ip,例化輸出,綜合時出現錯誤
ERROR:Xst:2035 - Port <clk> has illegal connections. This port is connected to an input buffer and other components.
查到的解決方法是禁掉自動I/O Buffer insertion 功能,具體的做法是右擊synthesize,然後properties->Xilinx Specific Options,把add I/O buffer 的勾去掉,綜合通過。但是這樣處理了之後在map時又引入了許多的warning,而且還會引發錯誤。方法出處一會轉帖出來。
(2)dac8812的控制時序測試時,綜合沒問題,但是map時出現錯誤
Pack:198 - NCD was not proced. All logic was removed from design.
其實這個錯誤的來源是下面的這幾個warning導致
MapLib:701 - Signal clk connected to top level port clk has been removed.
MapLib:701 - Signal dad connected to top level port dad has been removed.
以下省略很多這樣的warning,這個問題之前一直沒注意,後來才知道問題出在我在問題(1)中的處理,按照同樣的流程把add I/O buffer 勾上,綜合到route都沒什麼問題,可見warning也是不能忽略的呀。
(3)剛才不知道怎麼了,行為模擬的時候出現下面的error
ERROR:HDLParsers:3482 - Could not resolve instantiated unit dacinter in Verilog mole work/datest_top in any library
意思好像是找不到我top里例化的模塊了,重新添加了一下,好用了。
(4)行為模擬發現沒有波形,全是XX或者ZZZ,以前改一下clk頻率就好了,這回這招不好使了,後來嘗試改了一下rst的時間點,向後一段時間,發現好用了,模擬用的是ise自帶的simulation。
(5)綜合錯誤:ERROR:Xst:528 - Multi-source in Unit <entity> on signal <sig>
大多數時候應該是同一個變數,在兩個always模塊中賦值了。還查到一些其他情況,一並粘貼:
Solution 1
This error appears when XST determines that there is contention on a particular signal. If the processes assigning values to this signal are mutually exclusive (as in the case of 3-state buffers), this message can be ignored.
However, in most cases, XST is able to determine when multiple drivers are illegal, and will stop synthesis soon after this message.
Check this signal and modify your code to avoid the existing contention.
Solution 2
In some cases, XST ties unconnected output ports to ground. If the output port is part of a 3-state bus, which in turn connects to another 3-state bus, then connecting one bit of the bus to ground will cause a multiple-driver error. Verify that this is not occurring in your design by searching for the following warning:
"WARNING:Xst:1305 - Output <dataout<23>> is never assigned. Tied to value 0."
To work around this issue, remove the unused output port.
Solution 3
This has also been seen in the following condition:
When there is an association signal named to_qvm_d4.Q_num.
When using association signal(to_qvm_d4.Q_num), XST will rename it to "to_qvm_d4_Q_num" ring synthesis. There is signal named "to_qvm_d4_Q_num" in the same architecture. XST is confused with these two signals and errors.
To work around this issue, rename either of the two signals.
Solution 4
EDK Designs
For EDK Designs using bidirectional signals DIR=IO and THREE_STATE=FALSE, the external port name must match the connecting signal name exactly. NOTE: IOB_STATE is deprecated in future EDK versions.
(6)ERROR:Xst:902 - "dec_seg.v" line 38: Unexpected event in always block sensitivity list.
一個組合電路,綜合出錯,上網查說是敏感表中不能既有電平又有邊沿,而且也不能同一個信號的上升沿和下降沿同時出現,去掉敏感表中的邊沿,運行OK了。
(7)map的時候出現錯誤ERROR:Pack:679 - Unable to obey design constraints (LOC = ...) which require the combination of the following symbols into a single slice component:
檢查ucf文件,發現有一個管腳被重復分配,改了一下,運行OK!
(8)ERROR:NgdBuild:604 - 'GTP_DUAL_1' could not be resolved,這個錯誤在translate的時候報,是軟體的bug,網上查說ise12.2多發,但是我用的9.1也出了這個,原因大概是ISE只復制了頂層的NGC文件,即mycpu.ngc,而頂層mycpu還包含其它ngc文件,因此找不到,報錯。按照查到的解決辦法,有兩種。
解決辦法1是:在mycpu mole前面加上
(* box_type = "user_black_box" *)
如:
(* box_type = "user_black_box" *)
mycpu my_cpu_moudle (.fpga_0_clk_1_sys_clk_pin(sys_clk),
.fpga_0_rst_1_sys_rst_pin(sys_rst_n),
.fpga_0_RS232_RX_pin(uart_rxd),
.fpga_0_RS232_TX_pin(uart_txd),
.led_out_GPIO_IO_O_pin(led_out[0:3]));
辦法2是在ISE 的processes欄下,選中Translate,右鍵process propreties.....
彈出Translate Properties對話框,
在-sd macro search path 中加上EDK工程的implementation子目錄的路徑就可以了
一開始採用了第一種解決方案,translate通過,但在map時出錯。改用第二種,問題是,我用了兩個ip core,這個指定的路徑只能是一個最直接的目錄,所以只能完全解決其中一個core的錯誤,把兩個core的文件夾里的文件全拷到工程目錄中,指定工程目錄路徑為implementation子目錄路徑,搞定。
可以忽略的warning
(1)ProjectMgmt - "F:/verilogworks/FPGATESTS/datest_top_map.ncd" line 0 plicate design unit: 'Mole|datest_top'
5. Xilinx ISE錯誤 「MapLib:30 - LOC constraint......」
UCF文件中的管腳映射和實際中你在建工程所設定的FPGA板子型號中的管腳存在出入,比如,我昨天的工程中無意間選用了Zynq XC7Z100 封裝類型是FFG900,就會報這種錯誤,後面經層主點撥,在ISE的「Project」菜單欄下選「Dedign Properties...」中修改板子及封裝類型為Zynq XC7Z020 CLG484,問題解決。